1) Field of the Invention
This invention relates generally to a method for making integrated circuits and more particularly to the planarization of a shallow trench isolation (STI) high density plasma chemical vapor deposition (HDPCVD) isolation layer using chemical-mechanical polishing (CMP).
2) Description of the Prior Art
In fabrication of VLSI and ULSI integrated circuits, the use of fully recessed isolation, such as a process known as the "shallow trench" technique, has been used in submicron manufacturing processes to reduce surface topography related process problems associated with non-planar surfaces.
A typical structure would be formed in the following manner:
1. patterning and etching trenches in the field areas; PA0 2. passivating and filling the trenches with a dielectric material, typically an oxide, e.g. silicon dioxide; and PA0 3. planarizing the wafer surface. PA0 1 the non-conformal HDPCVD oxide layer 24--can fill wide and narrow trenches to a level about 500 .ANG. above the surface of the substrate PA0 2 The first and second nitride layers act as etch stops over more than 75% and more preferably more than 85% of the substrate area. This prevent dishing in all trenches. This also provides a better CMP STOP signal to the CMP machine thus over polishing is reduced. PA0 1 the first and second nitride layer are formed of LPCVD SIN and PECVD SIN respectively and a CMP ratio of PE-SiN to HDPCVD oxide is 2.5:1. This compares with a polish ratio of LP-SiN to HDPCVD oxide is 4:1.
There are numerous known methods of planarizing wafers during fabrication of integrated circuits, for example, block resist and resist etch back, block resist and spin on glass. A promising and simple method of choice is chemical mechanical polishing (CMP), CMP provides full wafer planarization without additional masking or coating steps. However, one of the difficulties encountered with CMP for trench planarization is the "dishing" effect which occurs in wide trenches (i.e. 10 .mu.m), typical of a fully recessed field structure. "Dishing" is particularly severe in trenches wider than 20 .mu.m and the "dishing" effect during polishing results in thinning of the dielectric in wide trenches only, and much effort has been directed to modify the polish process, equipment and materials attempt to reduce and control the dishing effect.
Moreover, the inventor has found dishing problems in narrow trenches. Also, the lack of polish stop layer over only portions of the substrate has worsened dishing effects and makes the polish endpoint less clearer. This leads to over polish problems.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,362,669(Boyd et al.) teaches a planarizing method for a conformal isolation layer 42.
U.S. Pat. No. 5,494,857(Cooperman et al) shows a STI CMP process.
U.S. Pat. No. 5,173,439(Dash et al.) discloses a STI CMP process.
U.S. Pat. No. 5,242,853(Sato et al.) teaches a ECRCVD STI fill and planarization process.
U.S. Pat. No. 5,728,621(Zheng et al.) shows a method of forming HDP oxide layers in STI and planarizing by using a SOG etchback process.
U.S. Pat. No. 5,4441,094(Pasch) shows a STI planarization process using a self-aligned poly mask.
U.S. Pat. No. 5,721,172(Jang et al) shows another self-aligned STI process using an etch.
C. Y. Chang, S. M. Sze, in ULSI Technology, by The McGraw-Hill Company, INC. copyright 1997, pp. 422-423, discusses HDPCVD oxide processes.